This invention relates to methods of manufacturing electronic devices comprising a thin-film transistor (hereinafter termed xe2x80x9cTFTxe2x80x9d) and provides improved processes for fabricating the TFT using self-aligned techniques. The device may be a flat panel display (for example, an active-matrix liquid-crystal display, AMLCD), or a large area image sensor or several other types of large-area electronic device (for example, a thin-film data store or memory device).
There is much interest in developing thin-film circuits with TFTs and other thin-film circuit elements on insulating substrates for large-area electronics applications. These circuit elements fabricated with portions of an amorphous, microcrystalline or polycrystalline semiconductor film may form the switching elements in a cell matrix, for example in a flat panel display as described in U.S. Pat. No. 5,130,829 (our reference PHB 33646), the whole contents of which are hereby incorporated herein as reference material. In more recent years, the devices may also include integrated drive circuits, particularly with TFTs of polycrystalline silicon (hereinafter termed xe2x80x9cpolysiliconxe2x80x9d) as the circuit elements.
In the fabrication of a polysilicon TFT, it is known to use implantation of dopant ions (e.g. phosphorus) to form a region for a source/drain of the TFT in a self-aligned (hereinafter termed xe2x80x9cSAxe2x80x9d) manner with a gate of the TFT. It is known to activate the implanted dopant and anneal the crystal lattice damage by directing an energy beam, particularly a laser beam, at the thin film structure.
The implanted region may be a highly doped drain region of the TFT. For a TFT used in a drive circuit, it can be advantageous to have a field-relief architecture comprising a low doped drain region (hereinafter termed xe2x80x9cLDDxe2x80x9d) between the channel and drain region of the TFT. In this case, the implanted SA region may be the LDD region, or it may be the higher doped drain region. Thus, there may be no significant overlap between the gate and the LDD region, or the gate may overlap the LDD region in a so-called GOLDD architecture. Unfortunately, it is found that the resulting SA TFTs can suffer from an increase in off-state leakage current and a reduction in carrier mobility.
The present invention seeks to provide manufacturing methods and fabrication processes for SA TFTs of electronic devices, that permit various improvements in the characteristics of the TFTs and of the devices with the TFTs.
More particularly, the invention provides a method of fabricating an electronic device comprising a thin-film transistor, comprising the steps of:
(a) depositing a gate layer over an insulating film, which is over a semiconductor film;
(b) defining a patterned mask layer over the gate layer;
(c) etching to pattern the gate layer using the mask layer;
(d) implanting the semiconductor film, using the mask layer and/or the gate layer as an implantation mask;
(e) etching back the gate layer under the mask layer;
(f) removing the mask layer; and
(g) annealing the semiconductor film with an energy beam.
In the case of TFTs with SA implanted regions, the inventors believe that an important: factor in increased off-state leakage currents and reduced carrier mobility is, lattice damage that extends beneath the edge of the gate and that is shielded by the gate from the laser anneal.
The mask layer may be a photoresist etchant mask, for example. The energy beam (particularly, but not exclusively, a laser beam) acts to anneal the implantation damage in the semiconductor film where not shielded/masked by the etched-back gate layer.
By this process, several of the problems due to implantation damage in SA polysilicon TFTs (with or without LDD or GOLDD) can be reduced or overcome or avoided.
Instead of the expression xe2x80x9cgate etch-backxe2x80x9d, other terms may be used such as xe2x80x9cgate over-etchingxe2x80x9d and xe2x80x9cgate undercutxe2x80x9d. Each expression refers to the etching process that results in an etched-back gate edge that is located under the mask layer so as to be offset/spaced from the edge of the mask window by a sufficient distance (gap) to permit the desired anneal of lattice damage in the intervening area. By controlling the extent of etching in step (c), the magnitude of the offset (gap) can be adjusted in accordance with the lateral extent of the semiconductor lattice damage as determined by different implantation dose levels.
The etch-back step (e) may be carried out after the implantation step (d). However, when the overlying mask pattern is thick and stable enough to mask the implantation by itself, then the step (e) can be carried out before step (d). Indeed this latter sequence has advantages. Laser annealing, (particularly, but not exclusively, with a UV excimer laser beam) is generally convenient for step (g). However, annealing with other types of energy beam may be used instead, e.g. using a high intensity UV flash lamp.
Although TFTs can be formed with other crystalline semiconductor materials, it is generally convenient to use polycrystalline silicon for the thin film semiconductor that provides the channel area of the TFT. The nature of the insulating substrate on which the TFTs are carried can vary, depending on the nature of the electronic device of which they form part. Typically the substrate may comprise a low-cost glass or an insulating polymer. Stainless steel may also be used.
In a preferred embodiment, etching steps (c) and (e) are carried out as a single processing step. This may provide more consistent results and more precise gap length control.
The method may include a further implantation step after step (f), providing a lower level of doping than step (d). This produces LDD regions between the source/drain regions formed in step (d) and the gate. This process may also be suitable for TFTs that operate at relatively low biases, that is, typically voltages up to approximately 5V. For these devices, a wider range of implantation doses may be employed in the further implantation step to reduce series; resistance, compared to doses normally used for creation of LDD field relief regions. Also, this technique allows the formation of shorter (typically sub-micron) LDD regions thereby reducing the series resistance of the region.
In another embodiment, step (b) comprises the steps of (h) defining a source/drain pattern mask layer; (i) performing an implantation step which provides a higher level of doping than step (d) to form source and drain regions defined by the source/drain pattern, with areas exposed only to the step (d) implantation forming LDD regions; and (j) patterning the mask layer to define a gate pattern. Alternatively, the method may include the further steps after step (c) of: (k) defining a source/drain pattern in another mask layer; and (I) performing an implantation step which provides a higher level of doping than step (d) to form source and drain regions defined by the source/drain pattern, with areas exposed only to the step (d) implantation forming LDD regions. Etch-back of the gate layer in these methods therefore creates gaps between the LDE regions and the edges of the gate layer. The implanted areas are fully exposed to the energy beam.
Another preferred method includes the steps of (m) defining an initial patterned mask layer; (n) performing an implantation step using the initial mask layer as an implantation mask, which implantation provides a lower level of doping than step (d) in regions extending laterally and inwardly beyond the edges of the patterned mask formed in step (b); and (o) annealing the semiconductor film with an energy beam. LDD regions can thus be formed which may extend under the gate of the finished device, in which the whole of the regions has been exposed to an energy beam to repair implant damage.
The method may include the step (p) of anodising the gate layer prior to etch-back step (e). Implantation step (d) is preferably carried out before step (p) as the step (d) may serve to harden the mask layer prior to the anodisation of step (p).
The gate layer may be of metal, or a semiconductor (e.g. polysilicon), or a combination of materials. Preferably, it comprises aluminium or a titanium and aluminium dual layer. The gate may be etched back in step (e) by a distance of 3 xcexcm or less, and more preferably, by 0.25 to 0.5 xcexcm.